Expect Intel's high-end chipset to show up next month
Intel officially set its performance embargo on its upcoming X38 Express chipset for September 23. Motherboards based on the X38 Express chipset should show up in retail in early September, according to motherboard vendors. The September 23 non-disclosure lift date only applies to reviews and performance numbers for the X38 Express chipset. The situation will be similar to the P35 Express chipset launch, where motherboards were available before its Computex 2007 launch announcement and NDA lift date.
The new chipset is a member of the Bearlake family, which saw its initial debut with the G33 and P35 Express variants last June. Intel's X38 Express succeeds the 975X Express that made its debut with Intel's Pentium D Presler processors. Although the Intel 975X Express launched in late 2005, the chipset shared basics with Intel's 945 and 955X Express chipset families. Intel decided not to refresh the 975X Express with a Broadwater variant and held out for Bearlake.
Intel's X38 Express introduces PCIe 2.0 support to the LGA775 platform. PCIe 2.0 offers greater bandwidth over the existing PCIe standard - up to four gigatransfers per second, or GT/s, with the 20% encoding overhead accounted for. The chipset also supports dual full-speed PCIe x16 slots for ATI CrossFire multi-GPU technology. Intel guidance does not show any indication of support for NVIDIA's SLI Technology.
Officially, the Intel X38 Express chipset only supports DDR3 memory. However, motherboard vendors disagree and intend to release X38 Express based motherboards with DDR2 memory support. Motherboard manufacturers such as DFI, Foxconn, Gigabyte, MSI and others had DDR2-compatible X38 Express motherboards on display at Computex 2007. The DDR2-compatible solutions were either DDR3 and DDR2 or dedicated DDR2 supporting motherboards.
Expect motherboards based on the Intel X38 Express to pop up in retail next month. DailyTech estimates the cost of entry around $200 for a no-frills board and around $300 for boards that include a kitchen sink in the package.
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The Intel i860 (also 80860) was a RISC microprocessor from Intel, first released in 1989. The i860 was (along with the i960) one of Intel's first attempts at an entirely new, high-end ISA since the failed Intel i432 from the 1980s. It was released with considerable fanfare, and obscured the release of the Intel i960 which many considered to be a better design. The i860 never achieved commercial success and the project was terminated in the mid-1990s.
The i860 combined a number of features that were unique at the time, most notably its VLIW (Very Long Instruction Word) architecture and powerful support for high-speed floating point operations. The design mounted a 32-bit ALU along with a 64-bit FPU that was itself built in three parts, an adder, a multiplier, and a graphics processor. The system had separate pipelines for the ALU, floating point adder and multiplier, and could hand off up to three operations per clock. (I.e., two instructions - one integer instruction and one floating point multiply-and-accumulate instruction per clock.)
All of the buses were 64-bits wide, or wider. The internal memory bus to the cache, for instance, was 128-bits wide. Both units had thirty-two 32-bit registers, but the FPU used its set as sixteen 64-bit registers. Instructions for the ALU were fetched two at a time to use the full external bus. Intel always referred to the design as the "i860 64-Bit Microprocessor".
The graphics unit was unique for the era. It was essentially a 64-bit integer unit using the FPU registers. It supported a number of commands for SIMD-like instructions in addition to basic 64-bit integer math. Experience with the i860 influenced the MMX functionality later added to Intel's Pentium processors.
One unusual feature of the i860 was that the pipelines into the functional units were program-accessible, requiring the compilers to carefully order instructions in the object code to keep the pipelines filled. In traditional architectures these duties were handled at runtime by a scheduler on the CPU itself, but the complexity of these systems limited their application in early RISC designs. The i860 was an attempt to avoid this entirely by moving this duty off-chip into the compiler. This allowed the i860 to devote more room to functional units, improving performance. As a result of its architecture, the i860 could run certain graphics and floating point algorithms with exceptionally high speed, but its performance in general-purpose applications suffered and it was difficult to program efficiently (see below).
Paper performance was impressive for a single-chip solution; however, real-world performance was anything but. One problem, perhaps unrecognized at the time, was that runtime code paths are difficult to predict, meaning that it becomes exceedingly difficult to properly order instructions at compile time. For instance, an instruction to add two numbers will take considerably longer if the data is not in the cache, yet there is no way for the programmer to know if it is or not. If you guess wrong the entire pipeline will stall, waiting for the data. The entire i860 design was based on the compiler efficiently handling this task, which proved almost impossible in practice. While theoretically capable of peaking at about 60MFLOPS for the XP versions, hand-coded assemblers managed to get only about up to 40MFLOPS, and most compilers had difficulty getting even 10.
Another serious problem was the lack of any solution to quickly handle context switching. The i860 had several pipelines (for the ALU and FPU parts) and an interrupt could spill them and require them all to be re-loaded. This took 62 cycles in the best case, and almost 2000 cycles in the worst. The latter is 1/20000th of a second, an eternity for a CPU. This largely eliminated the i860 as a general purpose CPU.
The chip was released in two versions, the basic XR (code named N10), and the XP (code named N11). The XP added larger on-chip caches, a second level cache, faster buses, and hardware support for bus snooping, for cache consistency in parallel computing systems. The XR ran at 25 or 40MHz, and a process shrink for the XP (from 1 micrometre to 0.8) bumped the XR to 40 and 50MHz. Both ran the same instruction set.
At first the i860 was only used in a small number of very large machines like the iPSC/860 at Los Alamos National Laboratory. As the compilers improved, the general performance of the i860 did likewise, but by then most other RISC designs had already passed the i860 in performance.
Intel for a time tested the viability of the i860 as a workstation CPU, competing with the MIPS Architecture chips and others. Microsoft initially developed what was to become Windows NT on internally-designed i860-based workstations (codenamed Dazzle), only porting NT to the MIPS (Microsoft Jazz), Intel 386 and other processors later. It is often rumoured that the original meanings of the 'N' and 'T' in Windows NT was for "N-Ten", after the working name for the i860 core.
The i860 did see some use in the workstation world as a graphics accelerator. It was used, for instance, in the NeXTdimension, where it ran a cut-down version of the Mach kernel running a complete PostScript stack. In this role the i860 design worked considerably better, as the core program could be loaded into the cache and made entirely "predictable", allowing the compilers to get the ordering right. Another example was SGI Onyx Reality Engine 2, which used a number of i860XP processors in its geometry engine. This sort of use slowly disappeared as well, as more general-purpose CPUs started to match the i860's performance, and as Intel turned its focus to Pentium processors for general-purpose computing.
In the late 1990s Intel replaced their entire RISC line with ARM-based designs, known as the XScale. Confusingly, the 860 number has since been re-used for a motherboard control chipset for Intel Xeon (high-end Pentium) systems.