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Thursday, October 4, 2007

ARM Cortex-M3

The ARM Cortex™-M3 32-bit RISC processor is the first ARM processor based on the ARMv7-M architecture and has been specifically developed to provide a high-performance, low-cost platform for a broad range of applications including microcontrollers, automotive body systems, industrial control systems and wireless networking. The Cortex-M3 processor provides outstanding computational performance and exceptional system response to interrupts while meeting low cost requirements through small core footprint, industry leading code density enabling smaller memories, reduced pin count and low power consumption.

The central core of the Cortex-M3 processor, based on a 3-stage pipeline Harvard bus architecture, incorporates advanced features including single cycle multiply and hardware divide to deliver an outstanding efficiency of 1.25 DMIPS/MHz. The Cortex-M3 processor also implements the new Thumb®-2 instruction set architecture, which when combined with features such as unaligned data storage and atomic bit manipulation delivers 32-bit performance at a cost equivalent to modern 8- and 16-bit devices.

The Cortex-M3 processor offers an excellent balance of architectural features, high performance and low costs, making it a very attractive choice for a broad range of applications, including:

32-bit performance at 8-bit costs
Wireless networking (inc Bluetooth, ZigBee and others)
Low power operation and integrated sleep modes supporting complex stacks
Automotive and industrial control systems
Secure, reliable and deterministic operation
White goods
High performance maths for complex motor algorithm support
Electronic toys
Low cost implementations for next generation intelligent toys
Medical instrumentation
High reliability core and tools enabling IEC61508 and FDA approval.

ARMv7-M architecture
The microcontroller profile of the ARMv7 architecture
Optimized for microcontroller and low-cost applications
Thumb-2 instruction set
Enhanced levels of performance, energy efficiency, and code density
Mixed mode capability implies no need to interwork between modes
ARM levels of performance with Thumb level code density
Hierarchical structure with tightly integrated peripherals
Harvard bus architecture – separate instruction and data buses
Highly efficient 3-stage pipeline with branch speculation
Nested Vectored Interrupt Controller (NVIC)
Gate efficient stack-based register model
Configurable from 1-240 physical interrupts; up to 256 levels of priority
Non-Maskable Interrupt (NMI) enables critical interrupt capabilities
Low latency through tail chaining, late arrival service & stack pop pre-emption
Nesting (stacking) of interrupts
Dynamic interrupt reprioritization
Memory Protection Unit (MPU)
Optional component for separation of processing tasks and data protection
Up to 8 regions of protection; each of which can be divided into 8 sub-regions
Region sizes between 32 bytes to the entire 4 gigabytes of addressable memory
Embedded Trace Macrocell(ETM)
Optional component for real-time instruction trace
Data Watchpoint and Trace unit (DWT)
Implements hardware breakpoints and provides instruction execution statistics
Flash Patch and Breakpoint unit (FPB)
Implements 6 program breakpoints and 2 literal data fetch breakpoints
Debug Port ( SW-DP or SWJ-DP )
Configurable debug access through Serial Wire or JTAG interface
Single cycle multiply and hardware divide instructions
32-bit multiplication in a single cycle
Signed and unsigned divide operations between 2 and 12 cycles
Preconfigured memory map
Up to 4 gigabytes of addressable memory space
Predefined addresses for code, memory, external devices, peripherals
Dedicated space for vendor specific addressability
Atomic bit manipulation with bit banding
Direct access to single bits of data
Two 1MB bit banding regions for memory and peripherals mapping to 32MB alias regions
Atomic operation, cannot be interrupted by other bus activities
Unaligned data storage and access
Continuous storage of data requiring different byte lengths
Data access in a single core access cycle
Integrated sleep modes
Sleep Now mode for immediate transfer to low power state
Sleep on Exit mode for entry into low power state after the servicing of an interrup
Ability to extend power savings to other system components
Fully synthesizable and highly configurable
Easily customized for broad applicability
For more details on the CM3Core please click here.
For more detalis on the NVIC please click here.


High performance
1.25 DMIPS/MHz on the Dhrystone 2.1 Benchmark
70% more efficient per MHz vs. the ARM7TDMI-S processor executing Thumb instructions
35% more efficient per MHz vs. the ARM7TDMI-S executing ARM instructions
Highly deterministic, low latency interrupt handling
Excellent data manipulation capabilities via Thumb-2 Bit Field Instructions
Low manufacturing costs
Low gate count implementations
33K gates Central Core (CM3Core)
60K gates or lower for complete standard implementation
Additional gate count reductions available through synthesis
All numbers for TSMC 0.18um G process, 50MHz target frequency
Smaller memory requirements
Up to 45% smaller code size vs. the ARM7TDMI-S executing ARM instructions
Up to 10% smaller code size vs. the ARM7TDMI-S executing Thumb instructions
Reduced pin count for lower packaging costs
Serial Wire Debug implements debug with just 2 pins
Single Wire Viewer implements single pin trace profiling
Enhanced energy efficiency
Clock gating, integrated sleep modes reduce power at no loss of performance
Power as low as 0.085 mW/MHz on the TSMC 0.13G process
Faster time to market with ease of use – system design
Fully synthesisable design
NVIC configurable to 1-240 physical interrupts with up to 256 levels of priority
Optional ETM can add trace capabilities
Optional MPU can add memory protection
Integrated debug/trace facilitate quicker debug
Faster time to market with ease of use – software development
Simplified stack-based programmer’s model ; simple vector based interrupt scheme
Thumb-2 removes need for interworking required by ARM/Thumb instructions
Native bitfield manipulation, hardware division and If/Then instructions
Thumb-2 is backwards compatible with existing ARM and Thumb solutions
Thumb-2 is compatible with other members of the Cortex family
The processor implements the stack manipulation in hardware
Hence assembler wrappers for handling stack manipulation for interrupt service routines are not necessary
NVIC integrates a systemtick timer that can provide an ideal heartbeat for a RealTime OS
ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models
Excellent 32-bit migration choice for 8/16 bit architecture based designs
Simplified stack-based programmer’s model is compatibile with traditional ARM architecture and retains the programming simplicity of legacy 8 and 16-bit architecture
Comparison of Cortex-M3 processor with ARM7TDMI® processor

The Cortex-M3 processor offers enhanced features and performance and an easy migration path to present a logical upgrade for ARM7TDMI processor-based designs desiring to meet the challenges of next generation technologies. The central core offers higher efficiency; a simpler programming model and excellent deterministic interrupt behaviour, whilst the integrated peripherals offer enhanced performance at lower cost and power consumption.

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