Search This Blog

Thursday, September 6, 2007

Nanotech initiative aims to reduce cost, power usage of embedded microchips

Houston's Rice University and Singapore's Nanyang Technological University announced on Sept. 4 an initiative dubbed The Institute for Sustainable Nanoelectronics, a joint effort aimed at lowering the cost and power consumption of embedded microchips with nanoscale solutions. ISNE is being funded by $2.6 million in seed money from NTU and is based at the Singapore institution.
The centerpiece to the initiative is the probabilistic CMOS (complementary metal-oxide semiconductor) chip invented by Rice researcher Krishna Palem, the architect of the ISNE initiative. PCMOS chips can tolerate nanoscale defects with a tunable numerical precision that trades off errors for lower power consumption. Last year Palem demonstrated a cell phone display [] in which no appreciable difference in picture quality could be detected by the naked eye, even when the PCMOS was tuned to use five times less power than conventional embedded chips.

ISNE will capitalize on the fact that for small screens, today's graphics chips are over-engineered, and that the brain's ability to perceive less-than-perfect images enables PCMOS and similar nanoscale technologies to harness defects and reproduce indistinguishable results at lower cost and using less power. The ISNE charter also calls for platform-independence in design methodologies, so that other nanotechnologies, such as photonics, can similarly benefit from trading off precision for lower cost and power.

Palem will direct his work with the International Network of Excellence - a team of computing experts from educational institutions like Rice University, NTU and Georgia Institute of Technology - from Rice, where he recently moved from Georgia Tech. The ISNE will also partner with Rice's new Value of Information-based Sustainable Embedded Nanocomputing Center, which Palem recently established with seed funding from Rice.

More power save

Chip scheme saves power

Portland, Ore. -- As CMOS integrated circuits shrink, parameter variations--slight differences among transistors that were designed to be identical--increasingly plague semiconductor designers. At the same time, the ability to cram in more and more transistors is making chips hotter. Now a new architectural technique called probabilistic systems-on-chip offers a comprehensive framework for solving both problems at once.

"Platforms that use our architecture will have a new design parameter--the probability of errors--which can be traded off for significant energy savings," said Krishna Palem, an EE professor at the Georgia Institute of Technology and founder of the university's Center for Research in Embedded Systems and Technology. "The key to our approach is a novel voltage-scaling scheme called biased voltage scaling, which can trade off energy consumption for signal-to-noise ratio in a well-defined manner."

Palem recently designed a probabilistic arithmetic unit for computing a fast Fourier transform (FFT) for a synthetic-aperture radar application. The work won the Best Paper award at last month's Cases 2006 conference in Seoul, South Korea.

Now Palem has fabricated the first hardware chip to demonstrate the probabilistic CMOS (PCMOS) technology for probabilistic applications with the Nanyang Technological University in Singapore. PCMOS defines parameter variations in devices, and their resultant error-prone circuit behaviors, as noise.

Palem began his work with applications that are inherently probabilistic anyway. "We have already shown enormous gains--300 to 400 times--for applications that exhibit a natural need for probabilities, such as neural networks, Baysean reasoning networks, pattern recognition, speech recognition and the like," he said.

Due to parameter variations between devices that will be unavoidable at the nanoscale, chip designers can expect all semiconductor behaviors to become probabilistic by 2016, according to the International Technology Roadmap for Semiconductors. To prepare for that future, Palem has begun developing probabilistic approaches to ordinary applications.

"Now we are looking at applications that operate on audio and video data streams, but which are not normally associated with probability--such as signal processing, filters and Fourier transforms," said Palem. "In this way, we have extended our probabilistic approach to encompass conventional computational primitives such as adders and multipliers."

To realize the probabilistic system-on-chip architecture, biased voltage scaling treats transistors differently, depending on where they are being used in a circuit. In the synthetic-aperture radar application, for example, "Error in the output of our probabilistic adder manifests itself as degradation in the signal-to-noise ratio of the radar image that is reconstructed by the FFT algorithm," said Palem. "In return for this degradation, which is visually indistinguishable from a reconstruction using conventional approaches, we realized a 5.6x energy savings."

Today voltage scaling is used to lower chip power consumption by lowering operating voltages (power equals voltage times current). For instance, lowering the operating voltage from 3.3 to 1.1 volts would achieve a threefold lowering of power consumption. Unfortunately, lowering operating voltage so close to the noise floor will also increase the probability of errors in the circuitry.

Palem's approach solves that problem by biasing voltage scaling toward parts of a circuit where errors can be tolerated. For instance, in an adder or multiplier, the operating voltage is dropped all the way to 1.1 V only for the least-significant bits, and is correspondingly increased for each more-significant bit; the most-significant bit is kept at full operating voltage.

"Using this approach, we have found that the amount of energy saved is seven times more than the lower signal-to-noise ratio we traded in to achieve it," said Palem.

Palem has fabricated the first hardware chip to demonstrate PCMOS with the Nanyang Technological University Singapore. The device, which is currently being packaged, has an input for a knob that can be twirled to adjust the trade-off between energy consumed and signal-to-noise ratio.

Next, the Georgia Tech researchers plan to incorporate the delays in on-chip signal paths as a source of probabilistic behavior. By incorporating probabilities calculations into carry-skip adder design, for instance, entire sections of carry propagation could be eliminated while simultaneously mitigating potential errors.

Technorati :

No comments:

Find here

Home II Large Hadron Cillider News