Search This Blog

Tuesday, March 18, 2008

Intel Talks Up Six Cores- new vector of graphics

Intel released a few incremental details about its future graphics chip on Monday, but left a lot of unanswered questions about the company's push into uncharted waters.

Larrabee, a "many-core" graphics processor scheduled for 2009 or 2010, will come with a brand-new set of vector-processing instructions as part of its design, said Pat Gelsinger, senior vice president and co-general manager of Intel's digital enterprise group. Vector-processing instructions are used to improve the performance of graphics and video applications; you may have heard of previous vector-processing implementations such as SSE4.

These new instructions, combined with Larrabee's compatibility with the x86 instruction set, will make life easier for software developers, according to Gelsinger. In addition to regular graphics tasks currently dominated by Nvidia and Advanced Micro Devices, Intel wants Larrabee to be able to take on a wider variety of tasks.

This is an emerging area of PC chip development--designing PC chips that use the best parts of graphics chips to improve performance. It's referred to by several names, with perhaps the most common label "GPGPU," or general-purpose graphics processing unit.

High-performance graphics chips are generally designed to do one thing, and do it fast. They aren't designed to handle the wide variety of workloads that PC chips tackle every day. As it becomes possible to add more and more cores to an individual chip, however, Intel, AMD, and Nvidia are investigating ways to build developer-friendly versions of graphics chips that can take on wider varieties of workloads.

The trouble is that "developer-friendly" line. Some of the current approaches for GPGPUs involve learning specialized programming techniques that are applicable just to that chip, and many of those are still very, very new compared with the 30-plus years of experience that people have had developing for the x86 instruction set.

"Attempts to create new programmable architectures are painful heavy-lifting over time, and for the most part they fail," said Gelsinger. And he should know: Intel's last attempt to create a new programmable architecture with the Itanium processor's EPIC instruction set hasn't come close to what Intel had once hoped to accomplish. Itanium hasn't been an abject failure, since people are buying the chips and development continues, but it's quite clear that Itanium is not, and will not be, the future of computing.

So this is Intel's pitch: it wants to get in on the graphics/multimedia game, since PC workloads are expected to head more and more in that direction. But it wants Larrabee to be like the release of a new Core 2 Duo processor: you'll have to learn how to use the new vector instructions to unlock the new performance, in the same manner you'd have to learn the new SSE4 instructions introduced last year with the Penryn chips, but you won't have to otherwise reinvent the wheel. Larrabee will also support familiar APIs (application programming interfaces) like DirectX and OpenGL, Gelsinger confirmed, an overview of the Nehalem microarchitecture that will replace Core as part of its "tock" strategy, and some tantalizingly vague details about Larrabee, the discrete graphics chip the company plans to release in either 2009 or 2010.
Dunnington will ship in the second half, said Pat Gelsinger, senior vice president and general manager of Intel's Digital Enterprise Group. Gelsinger, addressing media in San Francisco in a briefing on major topics on the slate for April's Intel Developer Forum in Shanghai, China, said the six-core CPU will be socket-compatible with the Santa Clara, Calif.-based chip maker's Caneland server/work station platform.

Featuring 16 MB of L3 cache and virtual machine migration technology called FlexMigration, Dunnington and Caneland will be "the industry's virtualization platform of choice for multi-processor servers," he said.

Intel's new microarchicture, Nehalem, will go into production in the fourth quarter, Gelsinger said. The first devices will be fabricated with Intel's 45-nanometer process technology, though a 32nm version of Nehalem codenamed Westmere is planned for 2009.

Nehalem features an integrated memory controller, bringing Intel's microarchitecture more in line with rival Advanced Micro Devices' "native" CPU design. AMD is in a race of its own to move to the 45nm process, which Intel achieved last year. A source close to Sunnyvale, Calif.-based AMD said OEMs and system builders expect 45nm sample devices from the chipmaker in the mid-Q3 timeframe.

The benefits of Nehalem, Gelsinger said, included increased parallelism, faster "unaligned" cache accesses, branch prediction enhancements and simultaneous multi-threading. Dual-core, quad-core and even octal-core Nehalem devices will roll out of the fab before the end of the year, he said.

Larrabee, Intel's latest attempt at discrete graphics, would theoretically challenge Nvidia and AMD's ATI division in the two top graphics chip makers' own superheated sandbox. According to Gelsinger, Larrabee represents Intel's "bold view of the transformation of visual computing."

But Gelsinger offered few details about Larrabee other than that it would arrive in 2009 or 2010, and that software developers inform him they are "really excited" about the multi-cored GPU's programmability. Or to be more accurate, really excited about what Intel says is the programmability of Larrabee -- no one has one of the devices yet, Gelsinger admitted.

A spokesperson for Santa Clara, Calif.-based Nvidia expressed doubts about a product that's at least a year away from shipment, if not considerably more.

"If you look at every other time they've launched a discrete graphics part, it's a failure. The reason why is that our rate of innovation is so much faster on the GPU side than theirs is," said the spokesperson.

"They're targeting this to come out in two years. That means they're not targeting anything moving," he said, noting that both Nvidia and AMD would both be in the midst of their own innovation cycles in the time period before Larrabee arrives.

No comments:

Find here

Home II Large Hadron Cillider News