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Sunday, September 16, 2007

NTU, Rice To Tackle Computer Chip Power Problems

NTU, Rice To Tackle Computer Chip Power Problems

Singapore's Nanyang Technological University (NTU) and Houston-based Rice University said they would form a research organization dedicated to resolving the power, heat, and current leakage issues that affect computer chips.

The Institute for Sustainable Nanoelectronics will focus on developing "next generation" integra that consume less than a hundredth of the energy that current models consume and will also be cheaper to conceptualize and produce.

NTU plans to contribute $2.6 million over the next two years to the Institute, which will be directed by Rice University computer science professor Krishna Palem.

NTU intends the Institute to "radically change the approach to chip design and evolve a design methodology that is platform-independent," Palem said.

"A major goal of this collaboration is to exploit the exponential rate at which the size of electronic components have been shrinking," he said. "The key is tying the costs for design, energy consumption and production to the value that the computed information has for the user."

MORE NEWS.......

A New Design for Computer Chips

Today, MIT spinoff Tilera announced that it's shipping a computer chip with 64 separate processors whose design differs drastically from that of the chips found in today's computers. The new chip, called Tile64, avoids some of the speed bottlenecks inherent in today's chip architecture, and it can operate at much lower power, says Anant Agarwal, founder and chief technology officer of Tilera, based in Santa Clara, CA. Initially, Tile64 will be used in video applications such as videoconferencing systems, and in network hardware that monitors traffic to reduce e-mail spam and viruses.

Chips with multiple processing units, or "cores," are nothing new. But by allowing the cores to communicate directly with each other, Tilera has addressed a widespread concern about the viability of adding more cores to microprocessors. "Every processor in the market today is a multicore," says Agarwal. "The hope of the industry is to double the number of cores every 18 months. My prediction is, by 2014, we will have 1,000-core architectures. But the problem is, [current] architectures don't scale."

In existing multicore chips, each core communicates with the others via a set of wires called a bus. Performance doesn't necessarily suffer when two or four cores share a bus, but when 16 or more cores try to use it simultaneously, data can get backed up. Agarwal explains that Tilera's chip has no central bus. Instead, each core is connected to all the others. Also on each core is a full-featured processor, which can run an operating system, and memory caches, which hold data that needs to be quickly accessed.

In effect, the Tile64 has a mesh structure that's similar to that of the Internet, a network in which there are many decentralized nodes. One reason the Internet is able to pass around data so quickly is that packets of information are sent through a vast network and can avoid traffic jams. If everyone's e-mail had to go through a central server, there would undoubtedly be delays. Tilera's microprocessor, says Agarwal, "is very much like the Internet on a chip." And like the Internet, Tilera's chip can be scaled up gracefully; it doesn't need to be redesigned each time new cores are added.

The idea of using mesh architecture for multicore chips has been explored for at least a decade, in research labs at MIT, Stanford, and the University of Texas, Austin. And recently, Intel announced a prototype 80-core chip based on a mesh. But Tilera is the first company to offer a product that uses the new architecture.

"Having a lot of cores is good, but they must be able to communicate with each other at high data rates," says Jerry Bautista, codirector of Intel's terascale-computing research program. "There are advantages to using a mesh ... You can deal with traffic jams pretty easily." Bautista says that Intel researchers are trying to find the best way to implement mesh architectures--among other experimental designs--in future chips. But he also cautions that making massively multicore systems work efficiently isn't as simple as redesigning the hardware.

We believe that to really get the most use out of these many-core systems, there's going to be quite a significant modification to the way people program today," Bautista says. The cores can handle many different instructions at once, he says, and software engineers will have to learn new programming techniques to take full advantage of the added computational capacity.

Tilera's Agarwal says that his company has addressed that concern by providing a software environment that helps customers gradually upgrade, debug, and optimize their applications to work on the 64-core system--even applications designed to run on a single core.

The company's technology is being presented this week at the Hot Chips symposium at Stanford, in Palo Alto. Nathan Brookwood, founder of Insight64, an analysis firm, says that many people at the conference are excited about Tilera's work, mainly because it could have immediate applications, such as expanding the capacity of videoconferencing systems and analyzing network traffic in routers. "I think they have a potential winner here," says Brookwood.

Intel's Bautista says the marketplace may be ready for a chip with more computing power, but it would need to be low power and easily programmed. He says that Intel will keep an eye on Tilera, as it does on many startups that are first to market with new technologies, to see how customers respond and which aspects of the technology could be improved. "We use companies like this to help us test the waters," he says.

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