Hydrogen Powered Vehicles steps forward with new meterial

Its not a dream that you are driving your car by water, Reseach is going forward and bringing us the posibility possible,
Researchers in Greece report design of a new material that almost meets the U.S. Department of Energy (DOE) 2010 goals for hydrogen storage and could help eliminate a key roadblock to practical hydrogen-powered vehicles.

Their study on a way of safely storing hydrogen, an explosive gas, is scheduled for the Oct. 8 issue of ACS' Nano Letters, a monthly journal.

Georgios K. Dimitrakakis, Emmanuel Tylianakis, and George E. Froudakis note that researchers long have sought ways of using carbon nanotubes (CNTs) to store hydrogen in fuel cell vehicles. CNTs are minute cylinders of carbon about 50,000 times thinner than the width of a human hair. Scientists hope to use CNTs as miniature storage tanks for hydrogen in the coming generation of fuel cell vehicles.

In the new study, the researchers used computer modeling to design a unique hydrogen-storage structure consisting of parallel graphene sheets — layers of carbon just one atom thick —stabilized by vertical columns of CNTs. They also added lithium ions to the material's design to enhance its storage capacity.

The scientists' calculations showed that their so-called "pillared graphene" could theoretically store up to 41 grams of hydrogen per liter, almost matching the DOE's target (45 grams of hydrogen per liter) for transportation applications.

"Experimentalists are challenged to fabricate this material and validate its storage capacity," the researchers note

Silicon Nanotubes For Hydrogen Storage In Fuel Cell Vehicles
After powering the micro-electronics revolution, silicon could carve out an important new role in speeding the debut of ultra-clean fuel cell vehicles powered by hydrogen, researchers in China suggest. Their calculations show for the first time that silicon nanotubes can store hydrogen more efficiently than their carbon nanotube counterparts.

Dapeng Cao and colleagues note that researchers have focused on the potential use of carbon nanotubes for storing hydrogen in fuel cell vehicles for years. Despite nanotubes' great promise, they have been unable to meet the hydrogen storage goals proposed by the U.S. Department of Energy for hydrogen fuel cell vehicles. A more efficient material for hydrogen storage is needed, scientists say.

In the study, Cao's group used powerful molecular modeling tools to compare the hydrogen storage capacities of newly developed silicon nanotubes to carbon nanotubes. They found that, in theory, silicon nanotubes can absorb hydrogen molecules more efficiently than carbon nanotubes under normal fuel cell operating conditions. The calculations pave the way for tests to determine whether silicon nanotubes can meet government standards for hydrogen storage, the scientists note.

The article "Silicon Nanotube as a Promising Candidate for Hydrogen Storage: From the First Principle Calculations to Grand Canonical Monte Carlo Simulations" will appear in the April 24 issue of ACS' Journal of Physical Chemistry C.

significant progress with its 3D-SIC (3D stacked IC) technology.

Test-chip taped for assessing design rules and models for 3D-SIC technology.

Significant Process In Creating 3D Stacked Integrated Chips

IMEC, Europe’s leading independent nanoelectronics research institute has announced that it has made significant progress with its 3D-SIC (3D stacked IC) technology. IMEC recently demonstrated the first functional 3D integrated circuits obtained by die-to-die stacking using 5µm Cu through-silicon vias (TSV).

It will now further develop 3D SIC chips on 200mm and 300mm wafers, integrating test circuits from partners participating in its 3D integration research program.
IMEC reported a first-time demonstration of 3D integrated circuits obtained by die-to-die stacking and using 5µm Cu through-silicon vias (TSV). The dies were realized on 200mm wafers in IMEC’s reference 0.13µm CMOS process with an added Cu-TSVs process. For stacking, the top die was thinned down to 25µm and bonded to the landing die by Cu-Cu thermocompression. IMEC is upscaling the process for die-to-wafer bonding and is on track for migrating the process to its 300mm platform.
To evaluate the impact of the 3D SIC flow on the characteristics of the stacked layers, both the top and landing wafers contained CMOS circuits. Extensive tests confirmed that the performance of the circuits does not degrade with adding Cu TSVs and stacking. And to test the integrity and performance of the 3D stack, ring oscillators with varying configurations were made, distributed over the two chip layers and connected with the Cu TSVs. Tested after the TSV and stacking process, these circuits demonstrated the chips excellent integrity.
“With these tests, we have demonstrated that our technology allows designing and fabricating fully functional 3D SIC chips. We are now ready to accept reference test circuits from our industry partners,” commented Eric Beyne, IMEC Scientific Director for 3D Technologies, “This will enable the industry to gain early insight and experience with 3D SIC design, using their own designs”.